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MP7226
BiCMOS Fixed, Quad, Voltage Output, Single or Dual Supply 8-Bit Digital-to-Analog Converter
FEATURES
* * * * * * * * * * *
APPLICATIONS
MPS Pioneered Segmented DAC Approach * Function Generators Four 8-Bit DACs with Buffer Amplifiers * Automatic Test Equipment Bipolar Amplifier Inputs for Low Noise and Drift * Process Controls Operates with Single or Dual Supplies BENEFITS P Compatible (95ns WR) No External Adjustments Required * Reduced Board Space; Lower System Cost Power-on-Reset Function * Reduced System Errors due to Excellent DAC-to-DAC Specified for 5 to 15 V Operation Matching and Tracking ESD Protection: 2000 Volts Minimum * Easy to Design with Microprocessors Latch-Up Proof * Stable, High Reliability through Advanced Processing Octal Available: MP7228 * Lower 1/f Noise Increases Useful Dynamic Range
GENERAL DESCRIPTION
The MP7226 contains four 8-bit voltage-output Digital-toAnalog Converters, with BiCMOS output buffer amplifiers and interface logic on a monolithic chip. Separate on-chip latches are provided for each of the four D/A converters. The control logic is speed compatible with most 8-bit microprocessors. All digital inputs are TTL/CMOS(5V) compatible.
The MP7226 is manufactured using advanced thin film resistors on a double metal BiCMOS process. The MP7226 incorporates a unique bit decoding technique yielding lower glitch, higher speed and excellent accuracy over temperature and time. The MP7226 maintains 8-Bit accuracy over the full operating temperature range without laser trim or external adjustments.
SIMPLIFIED BLOCK DIAGRAM
VREF VDD
- 1 +
LATCH 1 D A T A B U S
DAC 1
VOUT1
MSB DATA (8 BIT) LSB
LATCH 2
DAC 2
- 2 +
VOUT2
LATCH 3
DAC 3
- 3 +
VOUT3
LATCH 4 WR
DAC 4
- +4
VOUT4
A1 A0
CONTROL LOGIC
VSS
AGND
DGND
Rev. 2.00 1
MP7226
ORDERING INFORMATION
Package Type
Plastic Dip Plastic Dip PLCC PLCC SOIC SOIC
Temperature Range
-40 to +85C -40 to +85C -40 to +85C -40 to +85C -40 to +85C -40 to +85C
Part No.
MP7226KN MP7226LN* MP7226KP MP7226LP* MP7226KS MP7226LS*
INL (LSB)
1 1/2 1 1/2 1 1/2
DNL (LSB)
1/2 1/2 1/2 1/2 1/2 1/2
Full Scale Error (LSB)
1 1/2 1 1/2 1 1/2
*Contact factory for availability.
PIN CONFIGURATIONS
VOUT2 VOUT1 VSS VREF AGND DGND DB7 (MSB) DB6 DB5 DB4
See Packaging Section for Package Dimensions
3 2 1 20 19
1 2 3 4 5 6 7 8 9 10
20 19 18 17 16 15 14 13 12 11
VOUT3 VOUT4 VDD A0 A1 WR DB0 (LSB) DB1 DB2 DB3
1 2 3 4 5 6 7 8 9 10
20 19 18 4 5 6 7 8 18 17
See Pin Out at Left
17 16 15 14 13 12 11 9
See Pin Out at Far Left
16 15 14
10
11
12
13
20 Pin PDIP (0.300") N20
20 Pin SOIC (Jedec, 0.300") S20
20 Pin PLCC P20
PIN OUT DEFINITIONS
PIN NO. 1 2 3 4 5 6 7 8 9 10 NAME VOUT2 VOUT1 VSS VREF AGND DGND DB7 DB6 DB5 DB4 DESCRIPTION DAC 2 Voltage Output DAC 1 Voltage Output Negative Power Supply (0 V to -5 V) Reference Input Voltage Analog Ground Digital Ground Data Input Bit 7 (MSB) Data Input Bit 6 Data Input Bit 5 Data Input Bit 4 PIN NO. 11 12 13 14 15 16 17 18 19 20 NAME DB3 DB2 DB1 DB0 WR A1 A0 VDD VOUT4 VOUT3 DESCRIPTION Data Input Bit 3 Data Input Bit 2 Data Input Bit 1 Data Input Bit 0 (LSB) Write (Active Low) DAC Address Bit 1 DAC Address Bit 0 Positive Power Supply (+5 to +15 V) DAC 4 Voltage Output DAC 3 Voltage Output
Rev. 2.00 2
MP7226
ELECTRICAL CHARACTERISTICS
Single or Dual Supply Operation (VDD = +10.8 V to 16.5 V, VSS = 0 V or -5 V 10%, AGND = 0 V, DGND = 0 V, VREF = +2 V to +10 V, RL = 2k, CL = 100pF unless otherwise noted)
Parameter STATIC PERFORMANCE Resolution (All Grades) Integral Non-Linearity (Relative Accuracy) K L Differential Non-Linearity K L Total Unadjusted Error2 K L Full Scale Error3 K L Zero Code Error K L Output Load Resistance DYNAMIC PERFORMANCE4 Voltage Output Slew Rate Voltage Output Settling Time Digital Feedthrough Digital Crosstalk5 2 4 4 25 25 2 5 V/s s nVs nVs 2 N INL 1 1/2 DNL 1/2 1/2 2 1 1 1/2 20 15 2 3/4 3/4 LSB 2 1 LSB 1 1/2 mV 30 20 k 1 1/2 LSB 8 8 Bits LSB End Point Linearity Spec Symbol Min 25C Typ Max Tmin to Tmax Min Max Units Test Conditions/Comments
All grades monotonic over full temperature range.
VDD = 15 V 10%, VREF = +10 V
VREF = +10 V typ. Tempco is 5 ppm/C
TA = 25C typ. Tempco is 30V/C
VOUT = +10 V
VREF = +10 V; Settling Time to 1/2 LSB Code transition all 0s to all 1s VREF = 0 V, WR = VDD Code transition all 0s to all 1s VREF = +10 V, WR = 0 V
REFERENCE INPUT Reference Input Range1 Reference Input Resistance Reference Input Capacitance4 AC Feedthrough DIGITAL INPUTS Input High Voltage Input Low Voltage Input Leakage Current Input Capacitance4 Input Coding VINH VINL ILKG 2.4 0.8 1 8 2.4 0.8 1 8 V V A pF 1 2 500 -70 10 1 2 10 V k pF dB Limitation: VREF - VSS < 11 V Min RIN at Code 14910 Occurs when all DACs are loaded with all 1s VREF = 10 kHz, 5 V p-p sinewave
RIN
VIN = 0 V or VDD Binary
Rev. 2.00 3
MP7226
ELECTRICAL CHARACTERISTICS (CONT'D)
Parameter POWER SUPPLY VDD Range VSS Range (Dual Supplies)8 IDD ISS (Dual Supplies) 10.8 0 16.5 -5.5 12 10 10.8 0 16.5 -5.5 14 12 V V mA For specified performance For specified performance Outputs unloaded; VIN=VINL or VINH Outputs unloaded; VIN=VINL or VINH Symbol Min 25C Typ Max Tmin to Tmax Min Max Units Test Conditions/Comments
SWITCHING CHARACTERISTICS4, 6, 7 Address to WR Setup Time, t1 Address to WR Hold Time, t2 Data Valid to WR Setup Time, t3 Data Valid to WR Hold Time, t4 WR Pulse Width, t5 tAS tAH tDS tDH tWR 0 0 70 10 95 0 0 95 10 120 ns ns ns ns
NOTES: 1 VOUT must be less than VDD by 3.5 V to ensure correct operation. 2 Total Unadjusted Error includes zero code error, relative accuracy and full-scale error. 3 Calculated after zero code error has been adjusted out. 4 Sample tested at 25C to ensure compliance. 5 The glitch impulse transferred to the output of one converter (not adjusted) due to a change in the digital input code to another addressed converter. 6 All input rise and fall times are measured from 10% to 90% of +5 V, tR = tF = 5 ns. 7 Timing measurement reference level is (VINH + VINL)/2.
Specifications are subject to change without notice
Rev. 2.00 4
MP7226
ELECTRICAL CHARACTERISTICS
Single & Dual 5 V Supply Operation (VDD = +5 V 5%, VSS = 0 V to -5 V 10%, VREF = +1.25 V, AGND = 0 V, DGND = 0 V, RL = 2k, CL = 100pF unless otherwise noted)
Parameter STATIC PERFORMANCE Resolution (All Grades) Integral Non-Linearity (Relative Accuracy) K L Differential Non-Linearity K L Total Unadjusted Error2 Full Scale Error3 K L Zero Code Error Output Load Resistance DYNAMIC PERFORMANCE4 Voltage Output Slew Rate Voltage Output Settling Time Digital Feedthrough Digital Crosstalk5 2 4 4 25 25 V/s s nVs nVs 2 N INL 2 1 DNL 1 1 4 4 2 20 4 2 mV k VOUT = +10 V 1 1 LSB LSB 2 1 LSB 8 8 Bits LSB End Point Linearity Spec Symbol Min 25C Typ Max Tmin to Tmax Min Max Units Test Conditions/Comments
All grades monotonic over full temperature range.
VDD = 5 V 5%, VREF = 1.25 V VREF = +1.25 V
VREF = +1.25 V; Settling Time to 1/2 LSB Code transition all 0s to all 1s VREF = 0 V, WR = VDD Code transition all 0s to all 1s VREF = +1.25 V, WR = 0 V
REFERENCE INPUT Reference Input Range Reference Input Resistance Reference Input Capacitance4 AC Feedthrough DIGITAL INPUTS Input High Voltage Input Low Voltage Input Leakage Current Input Capacitance4 Input Coding VINH VINL ILKG 2.4 0.8 1 8 2.4 0.8 1 8 V V A pF 1 2 500 -70 1.6 1 2 1.6 V k pF dB VOUT must be < VDD by 3.2V Occurs when all DACs are loaded with all 1s VREF = 10 kHz, 1/2 V p-p sinewave
RIN
VIN = 0 V or VDD Binary
Rev. 2.00 5
MP7226
ELECTRICAL CHARACTERISTICS (CONT'D)
Parameter POWER SUPPLY VDD Range IDD ISS (Dual Supplies) 4.75 5.25 8 6 4.75 5.25 8 6 V mA For specified performance Outputs unloaded; VIN=VINL or VINH Outputs unloaded; VIN=VINL or VINH Symbol Min 25C Typ Max Tmin to Tmax Min Max Units Test Conditions/Comments
SWITCHING CHARACTERISTICS4, 6, 7 Address to WR Setup Time, t1 Address to WR Hold Time, t2 Data Valid to WR Setup Time, t3 Data Valid to WR Hold Time, t4 WR Pulse Width, t5 tAS tAH tDS tDH tWR 0 0 70 0 95 0 0 95 120 ns ns ns ns
NOTES: 1 VOUT must be less than VDD by 3.5 V to ensure correct operation. 2 Total Unadjusted Error includes zero code error, relative accuracy and full-scale error. 3 Calculated after zero code error has been adjusted out. 4 Sample tested at 25C to ensure compliance. 5 The glitch impulse transferred to the output of one converter (not adjusted) due to a change in the digital input code to another addressed converter. 6 All input rise and fall times are measured from 10% to 90% of +5 V, tR = tF = 5 ns. 7 Timing measurement reference level is (VINH + VINL)/2.
Specifications are subject to change without notice
ABSOLUTE MAXIMUM RATINGS (TA = +25C unless otherwise noted)1, 2
VDD to AGND, DGND . . . . . . . . . . . . . . . . . . . . . . 0 to +17 V Digital Input Voltage to DGND . . . . . . . . -0.5 to VDD +0.5 V VREF to AGND, DGND . . . . . . . . . . . . . . -0.5 to VDD +0.5 V VSS to AGND, DGND . . . . . . . . . . . . . . . . . . . . . +0.5 to -7 V AGND to DGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +1 V (Functionality Guaranteed +0.5 V) Storage Temperature . . . . . . . . . . . . . . . . . -65C to +150C Lead Temperature (Soldering, 10 seconds) . . . . . . +300C Package Power Dissipation Rating to 75C PDIP, SOIC, PLCC . . . . . . . . . . . . . . . . . . . . . . . . 900mW Derates above 75C . . . . . . . . . . . . . . . . . . . . . 12mW/C
NOTES: 1 Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation at or above this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. 2 Any input pin which can see a value outside the absolute maximum ratings should be protected by Schottky diode clamps (HP5082-2835) from input pin to the supplies. All inputs have protection diodes which will protect the device from short transients outside the supplies of less than 100mA for less than 100s.
Rev. 2.00 6
MP7226
D/A CONVERTER SECTION
The MP7226 contains four matched, 8-bit, voltage-mode Digital-to-Analog Converters (DACs) which incorporate an MPS pioneered unique bit decoding technique. This decoding scheme reduces the maximum binary weight carried by any resistor switch, reducing the accuracy required of the switches and resistor network. In the MP7226, the first three MSBs are decoded into three equal current sources, each contributing 25% of the full scale output current. Decoding two bits to three, a 1% change in any one of the converter's three decoded current sources affects the output by no more than 0.25% of full scale, compared with 0.5% in a conventional R-2R type CMOS DAC. The output voltages have the same polarity as the reference voltage, allowing single supply operation. The voltage reference range is from +2V to +10V. Each DAC uses a highly-stable, thin-film, ladder network and high-speed NMOS switches. Figure 1. shows a simplified circuit diagram for one channel.
- 2R 2R 2R VOUT +
4R
4R
4R
4R
4R
4R
VREF AGND 2 to 3 Decoder Switch Drivers
Shown for all 1s on DAC
Figure 1. Simplified D/A Circuit Diagram VREF Input
The VREF and AGND are common to all four DACs and set the full-scale output. The input impedance of the VREF pin is the parallel combination of the four individual DAC reference impedances and is code dependent. This impedance varies from 2k to 500k. Therefore, it is very important that the external reference source output impedance is low enough so that its output voltage will not be affected by the varying digital code. Due to transient currents at the VREF input during digital code changes, a 0.1F or greater decoupling capacitor on that VREF input is recommended. The input capacitance at the VREF pin is also code dependent and typically varies from less than 120pF to 350pF. Each VOUT voltage can be represented by a digitally programmable voltage source using the following expression : VOUT = Dn X VREF/256 where Dn is the decimal equivalent to the digital input code and can vary from 0 to 255. Rev. 2.00 7
Output Buffer Amp
Each D/A converter output is buffered by a unity gain noninverting BiCMOS amplifier which has slew rate greater than 2 V/ s . The output buffer settles to 1/2 LSB in less than 4s when driving a load of 2k in parallel with 100pF with a full scale transition from 0V to +10V or from +10V to 0V . The buffers can drive 2k and 500pF to 10V levels without oscillation. A simplified circuit diagram of the output buffer is shown in Figure 2. The Input stage is provided by BiCMOS PNP transistors with resulting lower input offset voltage, offset voltage drift over time and noise when compared to MOS process . The amplifier output stage uses a substrate NPN bipolar device to provide a low output impedance, high-output current capability. The MP7226 is specified for single or dual power supply operation, with only the buffer amplifier outputs using VSS supply current . Operating the MP7226 from dual supplies will improve the negative going output settling time near ground. In dual supply voltage operation , the output amplifier can sink 500A when VOUT = 0 V.
MP7226
VDD
A0 1 of 4 Decoder A1 To DAC1 Latch Enable To DAC2 Latch Enable To DAC3 Latch Enable To DAC4 Latch Enable
VIN Output
WR
AGND
VSS
Figure 3. Input Control Logic Figure 2. Simplified Output Buffer Amplifiers
The amplifiers outputs may be shorted to ground. However, the power dissipation of the package should not exceed the maximum limit. WR
H L L L L
A1
X L L L H H
A0
X L L H L H
Operation
No Operation; Device Not Selected DAC 1 Transparent DAC 1 Latched DAC 2 Transparent DAC 3 Transparent DAC 4 Transparent
Digital Inputs
All of the digital inputs to this DAC maintain TTL level interface compatibility and can also be driven directly with 5V CMOS logic inputs. The digital inputs are ESD protected to a rating of 2000 volts.
Digital Interface Logic
The MP7226 allows direct interface to most microprocessor buses without additional interface circuitry.
Table 1. Truth Table
tAS Address
tAH 5V 0V tWR 5V 0V tDS tDH VINH VINL 5V 0V
Figure 3. shows the input control logic circuit diagram and Table 1. shows the control logic truth table and operation for WR, A1, A0. The address lines A0, and A1 determine which DAC will accept the input data. The WR input determines whether the selected DAC is transparent (output follows the input), latched, or no operation. The WR input will also inhibit power on reset of the DAC latches to 0, if its initial state = 0 after 5 s of power. Figure 4. shows the write cycle timing diagram. When the WR signal is low, the input latch of the selected DAC is transparent, and the DAC's output corresponds to the value present on the data bus. On some data buses, data is not always valid for the entire period that the WR signal is low and can cause unwanted data at the output. Ensuring that the write pulse (WR) conforms to the data hold time, (t4) spec will prevent this problem.
WR
Data
NOTE: When the WR signal is low, the input latch of the selected DAC is transparent and any invalid data at this time will cause erroneous output.
Figure 4. Write Cycle Timing Diagram
Rev. 2.00 8
MP7226
APPLICATIONS INFORMATION
Digital Input Analog Output, VOUT
Power On Reset
11111111 At power up, all inputs are reset to 0 V if WR = 1. For WR = 0, the addressed DAC will receive input data. 10000001 10000000 01111111 00000001 00000000
Power Supply
The MP7226 can operate with either a single or dual power supply. Improved zero-code settling error can be obtained by using dual power supplies. The dual power supply specifications are a positive supply (VDD) range of +10.5V to +16.5V, and a -5V supply (VSS) . The single power supply specifications are a positive supply (VDD) range of +10.5V to +16.5V, or range of +4.75V to 5.5V . The specified reference voltage (VREF) range under these conditions is from +2V to VDD -4V. For those applications requiring +10V at the output (VREF = +10V), VDD must be +14V minimum to meet data sheet limits . 8-bit performance is guaranteed for single supply operation (VSS = 0V); however, zero code output sink capability is improved with VSS = -5V. For adequate DAC and Buffer operation, VREF must always be below VDD by at least 3.5V.
) V REF (255) 256 ) V REF (129) 256 V ) V REF (128) + ) REF 2 256 127) ) V REF ( 256 ) V REF ( 1 ) 256 0V
Note : 1 LSB + (2 *8) (V REF) + 1 (V REF) 256 Table 2. Unipolar Code Table
Digital Input
Analog Output
Power Supply Decoupling
11111111 The Power Supplies used with the MP7226 should be well regulated and filtered. Local power supply decoupling consisting of a 10F tantalum capacitor in parallel with a 0.01F ceramic is recommended. The decoupling capacitors should be connected between the VDD and AGND, and between VSS and AGND if VSS = -5V. 10000001 10000000 01111111 00000001 00000000
) V REF (127) 128 ) V REF ( 1 ) 128
0V
Unipolar Output Operation
In this configuration, the reference voltage is the same polarity as the output voltage. Since the reference voltage must always be positive with respect to GND, the output can only be 0 or positive.
* V REF ( 1 ) 128 * V REF (127) 128 * V REF (128) + * V REF 128
Table 2. shows the code relationship for the part in unipolar operation
Table 3. Bipolar Code Table
Rev. 2.00 9
MP7226
VREF R1 R2 VREF - DAC - + VOUT + VOUT
Bipolar Binary Operation
The Bipolar Mode configuration for each DAC requires one external op-amp and two resistors per channel.
Figure 5. shows a typical Bipolar Operation circuit using the MP7226. Table 3. shows the code relationship for the circuit of Figure 5. assuming R1 = R2 .
AC Reference Signal
VSS
AGND
VOUT = Dn X VREF X (1+R2/R1) - VREF X R2/R1 if R1 = R2 VOUT = VREF X (2Dn - 1) Where Dn is the digital input code and can vary from 0 to 255
Figure 5. Bipolar Output Circuit
+15 V
An AC signal can be applied to the reference of the MP7226 for multiplying capability within the upper (+10V) and lower (+2V) limits of the reference voltage input, with either single or dual supplies . This signal must be level shifted or AC coupled with proper bias level before being applied to the reference input. Figure 6. shows techniques for applying an AC signal to the MP7226. Since all four DACs share a common reference, they will all share this AC modulated reference. Input frequencies up to 50kHz will typically be distorted less than 0.1% .
+10 V +4 V AC Reference Input -4 V - + VOUT C R1 + R2 - DC Offset +2 V VREF VDD
DAC
DCOFFSET = VDD (+15) X R2/R1+R2
VSS -5 V or GND
AGND
Figure 6. AC Reference Input Signal Circuit (AC Couple)
Rev. 2.00 10
MP7226
R R
- DAC Output VOFFSET R + R VOUT
VOUT = Dn X VREF + VOFFSET where Dn is the digital input code and can vary 0 to 255
R
R
- DAC Output1 DAC Output2 R R VOUT +
VOUT = Dn1 X VREF + Dn2 X VREF where Dn is the digital input code and can vary 0 to 255
Figure 7. Digitally Programmable Offset Adjustment Circuits
AC Reference Input
+15 V + - VREF VDD
DAC DAC or DC Voltage
- +
VOUT
VSS -5 V or GND
AGND
Figure 8. Digitally Programmable AC Reference Input Signal Circuit (DC Couple) Offsetting DAC Outputs
Figure 7. shows examples of offset circuits.
buffer, the DAC output will begin to increment in a normal operation.
5V Operation DAC offset effects
When using the device in single supply applications, and minimum reference voltage, there is a possibility that the DAC output will not change when the code is incremented from 0. Once the DAC has reached the offset voltage of the output Rev. 2.00 11 The MP7226 can be operated with a single power supply (VDD = +5V ) or dual power supplies ( VDD = +5V and VSS = -5V) . The reference voltage range is reduced along with Some performance parameter degradation. However the DNL of each DAC remains at 1 LSB guaranteeing monotonicity.
MP7226
PERFORMANCE CHARACTERISTICS
Graph 1. Power Supply Current vs. Temperature
Graph 2. Relative Accuracy vs. Digital Code
Rev. 2.00 12
MP7226
20 LEAD PLASTIC DUAL-IN-LINE (300 MIL PDIP) N20
S
20 1 Q1 D
11 10 E1 E A1
Seating Plane
A L B e B1
C
INCHES SYMBOL A A1 B B1 (1) C D E E1 e L MIN -- 0.015 0.014 0.038 0.008 0.945 0.295 0.220 MAX 0.200 -- 0.023 0.065 0.015 1.060 0.325 0.310
MILLIMETERS MIN -- 0.38 0.356 0.965 0.203 24.0 7.49 5.59 MAX 5.08 -- 0.584 1.65 0.381 26.92 8.26 7.87
0.100 BSC 0.115 0 0.055 0.040 (1) 0.150 15 0.070 0.080
2.54 BSC 2.92 0 1.40 1.02 3.81 15 1.78 2.03
Q1 S Note:
The minimum limit for dimensions B1 may be 0.023" (0.58 mm) for all four corner leads only.
Rev. 2.00 13
MP7226
20 LEAD SMALL OUTLINE (300 MIL JEDEC SOIC) S20
D
20
11
E
H
10
h x 45 C Seating Plane e B A1 L A
INCHES SYMBOL A A1 B C D E e H h L MIN 0.097 0.0050 0.014 0.0091 0.500 0.292 MAX 0.104 0.0115 0.019 0.0125 0.510 0.299
MILLIMETERS MIN 2.464 0.127 0.356 0.231 12.70 7.42 MAX 2.642 0.292 0.483 0.318 12.95 7.59
0.050 BSC 0.400 0.010 0.016 0 0.410 0.016 0.035 8
1.27 BSC 10.16 0.254 0.406 0 10.41 0.406 0.889 8
Rev. 2.00 14
MP7226
20 LEAD PLASTIC LEADED CHIP CARRIER (PLCC) P20
D D1 A2 Seating Plane
1
D
D1 e1
B D2
D3 A
C A1
INCHES SYMBOL A A1 A2 B C D D1 (1) D2 D3 e1 Note: (1) MIN 0.165 0.100 0.148 0.013 0.008 0.385 0.350 0.290 MAX 0.180 0.110 0.156 0.021 0.012 0.395 0.354 0.330
MILLIMETERS MIN 4.19 2.54 3.76 0.330 0.203 9.78 8.89 7.37 MAX 4.57 2.79 3.96 0.533 0.305 10.03 8.99 8.38
0.200 Ref 0.050 BSC
5.08 Ref. 1.27 BSC
Dimension D1 does not include mold protrusion. Allowed mold protrusion is 0.254 mm/0.010 in.
Rev. 2.00 15
MP7226
NOTICE EXAR Corporation reserves the right to make changes to the products contained in this publication in order to improve design, performance or reliability. EXAR Corporation assumes no responsibility for the use of any circuits described herein, conveys no license under any patent or other right, and makes no representation that the circuits are free of patent infringement. Charts and schedules contains here in are only for illustration purposes and may vary depending upon a user's specific application. While the information in this publication has been carefully checked; no responsibility, however, is assumed for inaccuracies. EXAR Corporation does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reasonably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such applications unless EXAR Corporation receives, in writing, assurances to its satisfaction that: (a) the risk of injury or damage has been minimized; (b) the user assumes all such risks; (c) potential liability of EXAR Corporation is adequately protected under the circumstances. Copyright 1993 EXAR Corporation Datasheet April 1995 Reproduction, in part or whole, without the prior written consent of EXAR Corporation is prohibited.
Rev. 2.00 16

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